Sanyo ECR-238 - Page 24

14-2. DISPLAY AND KEY SCANNING CIRCUIT
The uPD75217CW has a built-in display controller
which reads out contents of the display memory and
automatically generates digit signal, segment signal
and a high voltage output buffer which can directly
drive fluorescent display tube. The output of digit
signals and segment signals is as follows.
}—_—— Display cycle —__—_-+4
Key scan timing
any
segment
SEGMENT SIGNALS / KEY SCAN TIMING
Key matrix is scanned by the segment drive signals of
display. As shown below one segment drive signal is
output in the last key-scan-timing of the display cycle
to scan one line of matrix. Every keys are scanned in
9 display-cycle.
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T0/Sdp_ YAY 1 1 f
Ti/Se
iT
LS
UC
T2/Sf
COA
Le
T7/Sa LS. U ie a
18.
aa
2
aE
t
{
Key
scan
Display
Timing
ae Ee
14-3. POWER FAILURE DETECTING CIRCUIT
This circuit detects the power failure or the power on
and generates PD signal to keep memory or to
prevent the circuit from erroneous operation which is
the unstable transient period of power supply.
The level of VPP (22V) drop when the AC power
supply is turned off when an instantaneous power
failure occurs.
The circuit detects the VPP failing down less than
some 13V and make the PD signal Low-level. On
receiving PD signal the CPU shelters the present
program counter and the contents of each register
from extinction. Also the CPU stops the clock
oscillation of X1 (4.19 MHz) to save the power
consumption. When the AC power is turned on, PD
signal is recovered High-level. CPU will active again.
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14-4. RESET CIRCUIT ©
This circuit generates RES signal. That reset signal
resets the CPU. This signal is generated by turning on
the AC power when the VCM voltage is lower than
about 2.4 volts. If the Ni-Cd battery voltage is normal,
this signal will not generate even if the AC power is off.
RAM access is inhibited during RES signal is low.
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