21
IC block diagram
1. Zoran ZR39670
Feature:
Embedded High Performance 300MIPS CPU
z Integrated MIPS 4KEc
TM
CPU, 300MHz
z Intended to run RTOS, audio decode and Application software
z 32-bit MIPS32 enhanced architecture
z 8 K instruction cache, 8 K data cache, (2-way set associative)
z MMU with 16-dual entry (TLB)
Integrated HDMI Link and PHY
z Two Independent instances of the PHY
z Support for HDMI v1.3
z Integrated Secure HDCP Keys
Integrated HD ADC
z Three YPbPr inputs (Two SCART)(Up to 1080p)
z One RGB input (Up to WUXGA)
z Up to 165 MHz input bandwidth
High-Performance MPEG-2 Video Decoding Engine
z Support for a single MP@HL decoder
Integrated Dual Channel LVDS Output for direct Panel Display support
z Supports up to 165MHz
z 1080p Output Flat Panel Support
z 100/120 Hz Operation with 768p panels
z 6, 8, 10 and 12-bit panel support
Integrated NTSC/PAL/SECAM Decoder
SCART Support
z Fast Blank/Fast switch inputs
z Video DAC for CVBS output
Display Processor & Controller
z PIP operation with Digital/Analog PIP
Common Interface (CI)
Integrated USB 1.1 Interface
System Interfaces
z Two 2-signal UARTs
z Three I2C master or Slave interfaces (up to 400 kb/s)
z One IR Receive, with hard N are demodulation
z Guest bus interface
z SPI interface
Device Unique Chip ID
z 128-bit device unique secret key
Memory Interface Unit
z High performance 32-bit DDR2 interface (400MHz)
z Up to 3.2GByte/second peak memory throughput
Process Technology
z 80 nm CMOS
Power
z 1.1 V core voltage 1.8 V Memory I/F, 3.3 V I/O
Packaging
z 35 mm x 35 mm Plastic Ball Grid Array package
z
632 BGA
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