Sanyo PLC-XF47 - Page 145

Command Decoder
Row decoder
Column Decoder &
Latch Circuit
Sense Amplire
Bank 0
Bank 1
Bank 2
Bank 3
Clock
Generator
Mode
Register
Control Logic
Column
Address
Buer
&
Burst
Counter
Data Control Circuit
Latch Circuit
Row
Address
Buer
&
Refresh
Counter
DQ
Input & Output Buer
DQM
Address
CLK
CKE
/CS
/RAS
/CAS
/WE
- 145 -
IC Block Diagrams
● EDS6416 (IC4101_5BNC_SLOT)
● 24C02CT (IC8195_DVI_SLOT)
Write-Protect
Circuity
YDEC
Sense Amp.
R/WControl
EEPROM
Array
HV Generator
XDEC
WP
Memory
Control
Logic
A0
A1
A2
SDA
SCL
Vcc
Vss