Sanyo PLV-Z4 - Page 90

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IC Block Diagrams
● PW386 <Scan Converter & Main CPU, IC301>
Display Timing
Generator
OSD
Control and Generation
Internal DRAM
MCKFBK,MCKFBKN,MCK,MCKN,MCKE,
MDM,MRAS,MCAS,MWE
MA(12:0), MD(31:0),
MDQS(3:0)
DHS
DVS
DEN
DCLK
Deinterlacer
IN0CLK
IN0PEN
IN0VS
IN0HS
IN0SOG
IN0VBI
IN0CST
IN0FLD
IN0CLP
IN0RGB(59:0)
IN1CLK
IN1PEN
IN1VS
IN1HS
IN1SOG
IN1VBI
IN1CST
IN1FLD
IN1CLP
IN1RGB(29:0)
Input Port 1
Sync Decoder
Auto Image Optimizer
Scaler
Video
Enhancement
Image Management
Video Enhancement
Color Space Converter
Image Blending
Display Port
Color Matrix, Gamma
CLTs,Color Space
Expander
DRGB(29:0)
Spread
Spectrum
PLL
XI XO
MCLK UCLK
PW386/PW386C
Internal Block Diagram
Frame Buffer Memory
Controller DDR SDRAM
Input Port 0
Sync Decoder
Auto Image Optimizer
VBI
Memory
Interface
Microprocessor Bus
PORTC(7:0)
PORTD(7:0)
PORTA(7:0)
PORTB(7:0)
NMI
RxD/
TxD
IRRCVR(1:0)
A(23:1),D(15:0)
BHEN,RD,WR
ROMWE,
ROMOE
CS(1:0)
GPIO PWM
Interrupt
Controller
2-Wire
Serial
IR
Decoders
UART
EXTINT(1:0)
Watchdog
& Timer
16-bit Turbo
Microprocessor
ROM
Interface
JTAG
TDO
TMS
TCK
TCI
VBI
Memory
Interface
● L3E07110 <Digital Gamma, IC401>
CONTRAST
BRIGHTNESS
GAMMA
CORRECTION
VIDEO SIGNAL
MASKING
H-CROSSTALK
CORRECTION
COLOR
SHADING
CORRECTION
GHOST
REDUCTION
CROSSTALK
CORRECTION-2
FRAME
MODULATION
SRAM
V-LINE
UNIFORMITY
LCCOM
CORRECTION
REFERENCE
VOLTAGE
INSERTION
SWAPPING
TIMING GENERATOR
10bit
10bit
10bit
SCS
SERIAL
INTERFACE
PATTERN
GENERATOR
DELAY
SCLK
SDATA
RIN[9:0]
BIN[9:0]
GIN[9:0]
OSDRIN[1:0]
OSDGIN[1:0]
OSDBIN[1:0]
OSDSW
OSD
PLL
HSYNC
VSYNC
DCLK
SELECT
R1OUT[9:0]
R2OUT[9:0]
G1OUT[9:0]
G2OUT[9:0]
B1OUT[9:0]
B2OUT[9:0]
CLXOUT(R:G:B)
DXOUT(R:G:B)
ENBX1-5(R:G:B)
HRESETO
HPLL
VRESETO
CLYOUT(R:G:B)
DYOUT(R:G:B)
FRP(R:G:B)
SHCLK(R:G:B)N
SHCLK(R:G:B)
XFR(R:G:B)
STSQE(R:G:B)
STQO(R:G:B)
NRG
SHENB
CLP1~2
DIRX(R:G:B)
DIRY
DIRX(R:G:B)N
ENBY1-2(R:G:B)
HSO VSO HSI VSI
R1
R2
G1
G2
B1
B2
10bit
10bit
10bit
10bit
10bit
10bit