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General| Operating System Support | Windows, Linux, macOS |
|---|---|
| Interface | USB |
| Supported Architectures | ARM, Cortex, RX, PowerPC, Renesas |
| Debug Protocols | JTAG, SWD |
| Voltage Range | 1.2V to 5.0V |
Specifies the necessary host and target system configurations for J-Link/J-Trace operation.
Lists the operating systems compatible with J-Link/J-Trace software.
Details the different models of J-Link and J-Trace available.
Compares hardware and software features across various J-Link/J-Trace models.
Lists the CPU cores that J-Link/J-Trace has been tested with.
Explains how J-Link supports CPU cores via firmware or PC-side intelligence.
Lists Integrated Development Environments (IDEs) compatible with J-Link/J-Trace.
Introduces J-Link licensing options and software enhancements.
Describes the three types of licenses: Built-in, Key-based, and Device-based.
Details the free, device-specific license activation process.
Provides a list of devices supported by the device-based license.
Lists original SEGGER products for which J-Link software is licensed.
Describes the J-Link product and its included licenses.
Details the J-Link Pro product and its comprehensive licenses.
Warns against and describes illegal J-Link clones and their prohibited use.
Provides an overview of J-Link software components and their descriptions.
Details the applications included in the J-Link software package.
Offers in-depth explanations of the J-Link software package components.
Explains the functionality and usage of the J-Link Commander tool.
Describes the TCP/IP server for remote J-Link/J-Trace access.
Details how to use J-Flash ARM for programming flash memory.
Provides details on additional software packages available.
Explains the J-Link SDK for custom application development.
Guides on utilizing the J-LinkARM.dll in applications.
Covers updating the J-LinkARM.dll in external programs.
Provides a step-by-step guide for installing the J-Link software package.
Explains how to set up and verify the USB connection for J-Link.
Guides on how to confirm the J-Link USB driver is installed correctly.
Provides instructions for uninstalling the J-Link USB driver.
Covers the configuration of the IP interface for network connectivity.
Explains configuration using the J-Link Configurator tool.
Introduces the J-Link Configurator utility for managing devices.
Step-by-step guide to configuring J-Links with the Configurator.
Explains methods for identifying J-Link devices via USB.
Guides on connecting multiple J-Links to a single PC.
Details the process of connecting J-Link/J-Trace to the target system.
Explains the meaning of the LEDs on the J-Link device.
Covers the usage and configuration of the JTAG interface.
Explains how to handle multiple devices in the JTAG scan chain.
Details the configuration options for JTAG speed.
Explains the Serial Wire Debug (SWD) interface and its usage.
Guides on performing multi-core debugging with J-Link.
Provides detailed steps for multi-core debugging configuration.
Highlights important considerations for multi-core debugging.
Overview of the J-Link control panel application.
Describes the different tabs available in the J-Link control panel.
Details the settings configurable within the control panel.
Covers settings related to flash download functionality.
Explains settings for flash breakpoint functionality.
Explains various reset strategies for target devices.
Details reset strategies specific to ARM 7/9 devices.
Details reset strategies for Cortex-M devices.
Guides on creating and using J-Link script files for customization.
Explains how to execute J-Link script files in different environments.
Covers customizing J-Link behavior using command strings.
Lists and describes available command strings for J-Link.
Command to select the target reset strategy.
Introduces the J-Link DLL's flash download feature.
Lists devices supported for flash download.
Explains setup for internal flash download in common debuggers.
Details setup for flash download in IAR Embedded Workbench.
Details setup for flash download in Keil MDK.
Explains setup for flash download using J-Link GDB Server.
Explains setup for CFI flash download in debuggers.
Setup for CFI flash in IAR EW / Keil MDK.
Introduces the flash breakpoints feature.
Covers licensing requirements for flash breakpoints.
Explains the 24-hour trial license for flash breakpoints.
Lists devices that support flash breakpoints.
Details setup and compatibility for flash breakpoints across debuggers.
Covers the setup process for flash breakpoints.
Lists debuggers compatible with flash breakpoints.
Introduces the Remote Debug Interface (RDI) standard.
Guides on setting up J-Link RDI with different debuggers.
Setup steps for using J-Link RDI with IAR Embedded Workbench.
Setup steps for using J-Link RDI with ARM AXD.
Setup steps for using J-Link RDI with ARM RVDS.
Setup steps for using J-Link RDI with Keil MDK.
Details the general configuration process for J-Link RDI.
Explains the options within the RDI configuration dialog.
Covers settings in the General tab of the RDI configuration.
Details settings related to flash programming in the RDI config.
Explains breakpoint settings in the RDI configuration.
Covers CPU-specific settings in the RDI configuration.
Lists specific MCUs from Analog Devices tested with J-Link.
Details specific handling for ADuC7xxx series MCUs.
Explains the software reset strategy for ADuC7xxx devices.
Lists specific devices from ATMEL tested with J-Link.
Details specifics for AT91SAM7 series, including reset and init.
Describes the reset strategy for AT91SAM7 devices.
Lists specific devices from Freescale tested with J-Link.
Covers the procedure to unlock Freescale Kinetis devices.
Lists specific devices from NXP tested with J-Link.
Details specifics for NXP LPC ARM7-based devices.
Provides a workaround for the Fast GPIO bug on LPC devices.
Lists specific devices from ST Microelectronics tested with J-Link.
Details specifics for STM32F10xxx devices.
Explains how to program option bytes for STM32 devices.
Covers securing and unsecuring STM32F10x devices.
Lists specific devices from Texas Instruments tested with J-Link.
Details specifics for AM335x devices, including IDE selection.
Guides on selecting the correct device in the IDE for AM335x.
Provides details and pinout for the 20-pin JTAG/SWD connector.
Details the JTAG pin configuration for the 20-pin connector.
Explains how to control target power supply via J-Link commands.
Provides the pinout for the SWD interface on the J-Link connector.
Details the 38-pin Mictor connector for JTAG and Trace.
Guides on connecting the target board using the 38-pin connector.
Provides the detailed pinout for the 38-pin Mictor connector.
Details the 19-pin connector for JTAG/SWD and Trace.
Explains target power supply for the 19-pin connector.
Describes the 9-pin connector for Cortex-M devices.
Lists available adapters for J-Link.
Provides background information on the JTAG standard and its components.
Explains the JTAG Test Access Port (TAP) functionality.
Describes the states and operation of the JTAG TAP controller.
Explains the Embedded Trace Macrocell (ETM) for debug and trace.
Details code tracing and data tracing capabilities of ETM.
Explains how flash programming works with J-Link.
Describes the mechanism of flash programming using J-Link/J-Trace.
Lists different solutions for flash programming.
Introduces J-Flash as a complete flash programming tool.
Explains using RDI flash loaders for download.
Covers information about the J-Link/J-Trace firmware.
Details the automatic firmware update process for J-Link/J-Trace.
Provides an overview of essential high-speed board design rules.
Explains the importance of balancing PCB track lengths for signal integrity.
Details methods for terminating trace signals.
Outlines the rules for applying series termination.
Lists the signal requirements for trace connections.
Discusses measuring and understanding download speed performance.
Offers solutions for common problems encountered with J-Link/J-Trace.
Provides a general step-by-step troubleshooting procedure.
Describes common issues and their remedies.
Troubleshooting steps when the J-Link LED is off.
Troubleshooting steps for a flashing J-Link LED.
Provides information on how to contact SEGGER support.
Lists common questions and answers related to J-Link usage.
FAQ about which CPUs are supported by J-Link/J-Trace.
FAQ regarding using J-Link within custom applications.
Defines adaptive clocking technique for JTAG/SWD.
Defines what a Dynamic Linked Library (DLL) is.
Defines Embedded Trace Macrocell (ETM) for ARM processors.
Defines the Joint Test Action Group (JTAG) standard.
Defines the Remote Debug Interface (RDI) standard.
Defines a scan chain in JTAG context.
Explains the semihosting mechanism for target-host communication.
Defines the JTAG TAP Controller's function.
Document defining the ETM standard, signal protocol, and physical interface.
Document describing ARM's RealView ICE emulator and target requirements.
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