Sharp FDD-412A - Page 41

FDD412A/B
2.6.4
Interface
Signal
Timing
This
section
discusses
the
timing
specifications
for
each
signal.
See
the
description
of
the
operating
principles
involved
for
the
operation and objective of each signal.
(1). WRITE GATE-N
ris-
WRITE
GATE-N
———4#——
i
'
Th
a
T2
eve
ee,
Fall
eRe
arto
I
ee
4
'
w— T3 —4 |
1
HEAD ENGAGE-N Pies stile
11 Ts.
! '
a) OFT, < 6us Ty, > 50 us
O< T2 < 6UuUs Ts > 580 Us
T3 > 50 ms Te’: Head loading off
Head change | aunsbicea area
Read/seek
Fig. 2.4] WRITE GATE Signal Timing
(2) WRITE DATA-N
1 0 1 1 0 0
- ant ele iy =
! Ts ‘ !
i
!
“a. 28 i!
ef sa
T; > 180 ns Ts > 180 ns
T2 > 180 ns Te > 180 ns
T3 = 1/2 Ts T7 = 2.0 ust0.1%
T, = 40us +0.1%
Fig. 2.42 WRITE DATA-N Signal Timing
(3)
LOW
CURRENT-N
WRITE
GATE-N
=|
it
1
1
—
Ti To! .
LOW
CURRENT-N
as
a
T, = T2 20
READ/WRITE
of
0%
43
TRACK:
‘'H!'
READ/WRITE
of
44776
TRACK:
'L'
Fig.
2.43
LOW
CURRENT
Signal
Timing