Sharp MZ-5600 - 6. I;O Decoder Logic; 6-1 Block Diagram

v) System switch
Table 2-4-a System . dip switch definition (MZ-5500)
Switch No.
SW1
SW2
SW3
l
SWS
OFF
ON
400 raster (1 D 10,11) CRT
200-raster CRT
Normal mode
Selfcheck mode
SW3
SW4 SWS
0
0
0
Standard MFD drive (S4B) DT/DD,
1 0
0
MZ-80BF
IF02,07,09
SW6
SW7
SW8
8086
Open
operated
to user
Reserved
8087 opera ted
Table 2-4-b System dip switch definition (MZ-S600)
Factory
Factüry
Description
setup
Description
setup
S\o11
OFF
High resolution OFF SW5
OFF 8MHz CPU clock
OFF '
display
(400
rasters) used
ON Medium resolution
ON
SMHz CPU clock
display
(200
rasters) used
SW2 OFF Normally OFF
SW6
OFF
8087 numerical
processor not
used ·
ON Seifeheck mode* ON 8087. numerical
processor used
SW3 Fixed to ON
ON SW7
SW4
-- -- --
Fixed to OFF
- ---
OFF SW8
System switches of the MZ-5500/5600 are assigned to functions shown in
Tables 2-3-a and 2-3-b. As these switches are assigned to bit, ID2 - ID7 of
the 1/0 address 60H for all models, they are sensed by the IPL at power on.
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