Sharp MZ-5600 - Page 46

6. DMA (*1)
6-1. DMA control with MZ-5500/5600
A different bus privilege acquiring method is used ' for the 8086 maximum ' mode
and minimum mode. In , the minimum mode, the use of the bus is requested with
HOLD by the peripheral unit, and gran ted with HLDA by th e 8086. In th e
maximum
mode, the perfpheral unit first sends the bus request pulse RQ to
the RQ/GT line, to which the 8086 sends the GT pulse on the same line to
grant the request. ~\en the bus has been released from the us~, the
peripheral unit sends a release pulse on the same line.
With theMZ-5500/5600, the DMAC is used for data transfer between the disk
and the memory and for DRAM refreshing. The hold request sequence of tlle
8237A(*2) is suitable for the minimum mode of the 8086. But it has to be
converted into HOLD and HLDA of the 8237A since the 8086 must be operate~ in
the maximum mode in order to interface with the 8087 Coprocessor. As this
conversion circuit is rather complicated, the conversion is done in the
f0110win~ mannet. When receiving HOLD from the 82J7A, the 8086 recogniz es
it at the end oE the bus access cyc1e or in the idle cycle, and returns lILDA.
Simultaneously, it is put into the non-ready condition and separated f rom
the wywtem bus, during which time the 8237A executes OMA transfer, and, uron
compl etio n, r e leases HOLD. In this manner, the 8237A deprives th e CPU of
the bus for six clocks. If the epu goes into th p- bus cycle after rp-c e i.ving
HOLD, w~its are inserted for six c10cks at , the maximum, and accessing is
continued thereafter as if nothing happenp-d.
As four channel$ are provided for the 8237A; channel 1 for the MFD, channel
2 for the RAM refresh, and channels, 0 and 3, for the 1/0 slot (expansion
slot), it is expected to use the channel 0 for exclusive use of the hard
disk and the channel 3 for other device. Discussion will be provided
separately in regard to the channel 3.
Although there are several modes for the DMA transfer with the 8237A, the
single transfer mode must be used in order to assure proper refreshing.
6-2. Operational theory
The 8237A Programmable DMA Controller has four independent DMA channels. The
ehannel 1 is for the standard MFD interface in which the DREQ delay circui.t i s
provided to meet the specification from DREQ to lORD of the FDC(*3). The
channel 2 i 's for refresh of the system RAM which is refreshed as the CTC
reads DRAM by means of arequest at every 13 mtcroseconds.
!8,MS .aan~
. iIJToo ---.fl nL-- __ _
=r~ '\ ~
-ro:nT Don't (ur, U ~~t ~
(*1): DMA
It is a short words for Direet Memory Aceess which the memory is read,
written, and refreshed without intervention of the CPU.
(*2): 8237A
It is the DMA controller whieh has four independent channels.
(*3): FDC
It i5 a short words for Floppy Disk Controller.
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