Method of operation7SV512
V1
35C53000---G1176---C91
Thus, release signal Rel2 is produced bythegeneral
fault detection signal of the main protection at BI 10
as long as no blocking signal is present at BI 8;
whereas anadditional general tripsignal of the main
protection must be present at BI 9 for the release
conditions Rel1 and Rel0.
The outputs of the trip release module are con-
nected such that Rel1 releases the triprelay K1,and
Rel2 releases the trip relay K2. It is assumed that K1
isused fortrip command tothe bus-bar breakers, K2
is intended for the intertrip signal to the remote line
end. The tripsignal ofthe main protection relayisnot
included for intertrip so that this relay can be used
also in case of end fault protection operation (refer
Section 4.3).
The remaining trip relay K3 to K5 are not equipped
with this special trip release feature. Of course, the
dual channel control with additional release transis-
tor which is usual for all trip relays is also valid for K3
to K5.
The correct operation of the trip release module is
supervised by the processor system. A choice can
be made whether adefect should cause the breaker
failure protection to be blocked, and after what time.
BI 8
External
blocking
BI 9
General
trip command
BI 10
Pl5
Pl4
to processor to processor
Trip release module
&
&
&
Pl1
from processor
K1
General
fault detection
Rel1
Rel0
Rel2
Pl2
Pl3
Trip
relays
K2
K3
to
K5
Figure 4.15 Trip release module (hardware module)
When a trip release signal appears without an initia-
tion signal caused by main protection trip, an inter-
nal fault must be present. After a (settable) time
delay TBLOCK---MON (Figure 4.16), the breaker fail-
ure protection can be blocked (parameter BLOCK---
MON). Blocking is also effective, when the current
sum monitoring I has recognized implausible devi-
ations (refer also Section 4.5.4.1). Note that the cur-
rent sum monitor can only operate correctly if four
currents (three phases and residual current) are fed
to the relay from the current transformers.
TBLOCK
MON
>
1
>
1
&
S Q
R
BLOCK---MON
YES
NO
internal
blocking
I mo-
nitor
HW---Rel.
Init L1
(acc.
Fig 4.11)
Init L2
Init L3
Figure 4.16 Blocking
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