Configuring/address space
4.4 On/Off delay mode
Technology Module TM Pulse 2x24V (6ES7138‑6DB00‑0BB1)
80 Manual, 05/2019, A5E35061186-AB
Pulse diagram
The following figure shows an example of an output sequence for the case that you set
SW_ENABLE while digital input DIn.0 is not set.
Figure 4-5 Example 1 of an output sequence
The output sequence starts on a positive edge of SW_ENABLE, and the STS_SW_ENABLE
and STS_ENABLE feedback bits are set. If digital input DIn.0 is set and remains set for the
duration of the input delay, the On delay is started. As soon as the On delay has elapsed,
the respective digital output DQn.A is set. If digital input DIn.0 is reset and remains set for
the duration of the input delay, the Off delay is started. As soon as the Off delay has
elapsed, the respective digital output DQn.A is reset.
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