S5-100U Introduction to STEP 5
Response Time
Response time t
R
is defined as the time between a change in the input signal and the subsequent
change in the output signal.
Prerequisites for the following information:
• No interrupts are running.
• The programmer interface is not in use. (The load is very dependent on the function.)
The response time is influenced by the following factors:
• The input module delay (see chapter 14)
• The program processing time (see Appendix A)
• The data cycle times (number of data bits x 25 µs - a bus configuration of 256 data bits results
in a data cycle time of approximately 8 ms)
• The operating system run time (up to 3% of the program cycle)
• The processing of the internal timers
T 0 to T15 for CPU 100
T 0 to T31 for CPU 102
T 0 to T127 for CPU 103
Calculating the maximum response time t
Rm
:
• With t
G
= 2 x program processing time + 3 x data cycle time + 3 x operating system run time
+ delay time of the input modules
• Maximum processing time of the internal timers t
Tm
t
Tm
= number of processed timers x 32 µs(number of processed timers for CPU 100: 16
number of processed timers for CPU 102: 32
number of processed timers for CPU 103: 128)
t
Tm
= 103 µs for CPU 103 version 8MA03
t
Rm
=t
G
( 1 + ) + t
Tm
.
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t
Tm
10 ms
During the transition from STOP to RUN, there is a one-time increase in the response time to about
200 ms.
Figure 7-14. Calculating the Response Time
Program processing
A I 0.0 = Q 1.0
Response
Input
module
delay
Time
I 0.0
Q 1.0
Data
cycle
1
0
1
0
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Data
cycle
EWA 4NEB 812 6120-02
7-27
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