Siemens S5-100U - Bit Test Operations, for CPU 103 and Higher

STEP 5 Operations S5-100U
8.2.3 Bit Test Operations, for CPU 103 and Higher
Bit test operations scan digital operands bit by bit and affect them. Bit test operations must always
be at the beginning of a logic operation. Table 8-12 provides an overview of these operations.
Table 8-12. Overview of Bit Operations
Operation Meaning
Test a bit for signal state “1”
A single bit is scanned regardless of the RLO. The RLO is affected
according to the bit's signal state (see Table 8-13).
Parameter
0.0 to 127.15
0.0 to 127.15
0.0 to 255.15
0.0 to 255.15
Operand
TB
TBN Test a bit for signal state “0”
A single bit is scanned regardless of the RLO. The RLO is affected
according to the bit's signal state (see Table 8-13).
ID
T
C
D
RS
1
SU
RU
Set a bit unconditionally
The addressed bit is set to “1” regardless of the RLO. The RLO is
not affected.
Reset a bit unconditionally
The addressed bit is set to “0” regardless of the RLO. The RLO is
not affected.
1
RS applies only to TB and TBN
Table 8-13 shows how the RLO is formed during the bit test operations “TB” and “TBN”. An
example for applying the bit operations follows the table.
Table 8-13. Effect of “TB” and “TBN” on the RLO
10
0 1
Operation TB TBN
Signal state of the bit in
the operand indicated
0 1
Result of logic operation 1 0
8-42 EWA 4NEB 812 6120-02