Technical specifications
A.6 CPU 1217C
S7-1200 Programmable controller
880 System Manual, 03/2014, A5E02486680-AG
Temporary (local) memory
• 16 Kbytes for startup and program cycle (including associated FBs and FCs)
• 6 Kbytes for each of the other interrupt priority levels (including FBs and FCs)
Communication module expansion
High-speed counters Up to 6 configured to use any built-in or SB inputs (refer to CPU 1217C Digital
input (DI) H/W configuration table) (Page 882)
• 1 MHz (Ib.2 to Ib.5)
• 100/
1
80 kHz (Ia.0 to Ia.5)
• 30/
1
20 kHz (Ia.6 to Ib.1)
Pulse outputs Up to 4 configured to use any built-in or SB outputs (refer to CPU 1217C Digital
output (DQ) H/W configuration table) (Page 882)
• 1 MHz (Qa.0 to Qa.3)
• 100 kHz (Qa.4 to Qb.1)
4 total with 1 ms resolution
4 total with 1 ms resolution
12 rising and 12 falling (16 and 16 with optional signal board)
SIMATIC Memory Card (optional)
Real time clock retention time
20 days typ./12 days min. at 40 °C (maintenance-free Super Capacitor)
1
The slower speed is applicable when the HSC is configured for quadrature mode of operation.
Table A- 89 Performance
Boolean 0.08 μs/instruction
Real math 2.3 μs/instruction
Timers, counters and code blocks supported by CPU 1217C
Table A- 90 Blocks, timers and counters supported by CPU 1217C
Blocks
Up to 1024 blocks total (OBs + FBs + FCs + DBs)
Address range for FBs, FCs,
and DBs
FB and FC: 1 to 65535 (such as FB 1 to FB 65535)