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Product Information on the Manual S7-300 Module Specifications, Edition 11/2002
A5E00213444-02
1.1 Clock synchronization
Characteristics
Reproducible response times (i.e. times of the same length) are achieved in
SIMATIC by means of an equidistant DP bus cycle and the synchronization of the
following free-running individual cycles:
S Free-running cycle of the user program. On account of cyclic program branches
the length of the cycle time may vary.
S Free-running, variable DP cycle on the PROFIBUS subnet.
S Free-running cycle on the DP slave backplane bus.
S Free-running cycle at signal conditioning and conversion in the electronic
modules of the DP slaves.
With equidistance the DP cycle runs with the same clock pulse and for the same
length. The priority classes of a CPU (OB 61 to OB 64) and the clocked I/Os are
synchronized with this clock pulse. The I/O data are thus transferred at defined,
fixed intervals (clock synchronization).
Prerequisites
S The DP master and DP slave must support clock synchronization. STEP 7 as of
Version 5.2 is required.
Mode: clock synchronization
The following conditions apply to clocked mode:
Filter and processing time T
WE
between the actual values being read in
and made available in the transfer buffer
(the specified value for T
WE
applies regardless of the activation of the
hardware interrupt or diagnosis)
255 to 345 ms
Includes an input delay of 100 ms
T
DPmin
2.5 ms
Diagnostic interrupt max. 4 x T
DP
Note
In clocked mode, the input delay of the inputs is always 100 ms, regardless of the
input delay parameterized in STEP7.
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