Siemens SIDOOR ATD401W - On Delay Block; Counter Block




+,*+/2:
9
7
W
W
RQ
W
RII
① Input signal
② Output signal
③ The output signal changes after 3 detected signal periods after the 4th edge
• An input tolerance of (±) 40 ms is assumed.
• Duty cycle: 20 % (17 to 23 %)
• 1 Hz frequency detection:
– T = 1000 ms (±2 %)
– t
on
= 200 ms
– t
o󹪜
= 800 ms
– Pulse/pulse ratio V = 25 %
• 0.5 Hz frequency detection:
– T = 2000 ms (±2 %)
– t
on
= 400 ms
– t
o󹪜
= 1600 ms
– Pulse/pulse ratio V = 25 %
Figure 4-10 Frequency-based input signal detection
The outputs Q24 or Q26 become active when the analysis algorithm detects a frequency of 1 Hz
with a 20 % duty factor in the input signal. The outputs Q25 or Q27 become active when the
analysis algorithm detects a frequency of 0.5 Hz with a 20 % duty factor in the input signal.
The maximum response time at the output, i.e. the time after which the system can detect an
error or a deviation in the input signal frequency, corresponds to the period of the frequency to
be detected. Accordingly, a frequency of 1 Hz results in a maximum response time of 1 s and a
frequency of 0.5 Hz results in a maximum response time of 2 s.
4.3.9.9 On delay block
The "OnDELAY" block delays the input signal at the output Q28 by 2 s and at the output Q29 by
5 s.
4.3.9.10 Counter block
The "COUNTER" block increments the internal counter value in the event of a positive edge at the
input.
SIDOOR functions
4.3 Extended functions
ATD4xxW for industrial applications
100 System Manual, 06/2022, A5E51901827B AA