Blocks of the library
5.2 Explanation of SIMATIC STEP 7 blocks
SITOP PSU8600 Firmware V1.3: Faceplates and Communication Blocks V2.3 for SIMATIC STEP 7 V5.5
Function Manual, 11.2017, A5E37764016-06-76
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Table 5- 11
Bool On the rising edge (0 > 1), data at the
inputs of the block is written to the
WORD Start address of the entire main mod-
WORD Output address of main module I/O
UDT for device input parameters.
Structure of UDT_General_PSU_IN_V2 data type
Table 5- 12
BYTE During a network failure, output 1 of the main module
can be supplied with priority.
BYTE Switch-on behavior.
0 = no switch-on delay
1 = switch-on delay of 25 ms
2 = switch-on delay of 100 ms
3 = load-optimized switch-on delay
4 = variable switch-on delay
Pre-alarming threshold (0 to 100 %) for alarming.
BYTE Outputs 1 and 2 are switched parallel. Output 2 fol-
lows output 1. (Values for output 2 are ignored.)
BYTE Outputs 3 and 4 are switched parallel. Output 4 fol-
lows output 3. (Values for output 4 are ignored.)
BYTE Outputs switched off due to overload are switched on
again, if they are ready for it.
0 = normal state (no actions taken)
1 = switched on again (attention, the value must be
reset to 0 after switching on.)
System overload alarm threshold time (0 to 60000 ms)
WORD Main power outage alarm threshold time