Blocks of the library
5.2 Explanation of SIMATIC STEP 7 blocks
SITOP PSU8600 Firmware V1.3: Faceplates and Communication Blocks V2.3 for SIMATIC STEP 7 V5.5
40 Function Manual, 11.2017, A5E37764016-06-76
Table 5- 29
BOOL On the rising edge (0 > 1), data at the
inputs of the block is written to the
WORD Start address of the entire main mod-
WORD Output address of main module IO
UDT for device input parameters
Structure of UDT_General_PSU_S_IN_V2 data type
Table 5- 30
BYTE During a network failure, output 1 of the main
module can be supplied with priority.
BYTE Switch-on behavior.
0 = no switch-on delay
1 = switch-on delay 25 ms
2 = switch-on delay 100 ms
3 = load optimized switch-on delay
4 = variable switch-on delay
Pre-alarming threshold (0 to 100 %) for alarming.
BYTE Outputs switched off due to overload and are
switched back on if they are ready for it.
0 = normal state (no actions taken)
1 = switched back on (attention, the value must
be reset to 0 after switching on.)
BYTE Soft output characteristics (False = 0, True = any
WORD System overload alarm threshold time
WORD Main power outage alarm threshold time