SIMATIC STEP 7 function blocks
5.13 FB SITOP_PSU8600_Buffering_1
SITOP PSU8600 Firmware V1.4: Faceplates and Communication Blocks V2.4 for SIMATIC STEP 7 V14 SP1, V15 and V15.1 (TIA)
Function Manual, 11.2018, A5E37763954-09-76
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Bool On the rising edge (0 > 1), data at the inputs of
the block is written to the PSU.
HW_IO Start address of the entire main module.
(Reference, system tag: here, "PSU_1" refers to
the already assigned PROFINET device name of
memory_address
HW_IO Address of main module IO data submodule.
(Reference, system tag: <PSU Device
Name>~PSU8600_IO_Data_submodule. For
example:
PSU_1~PSU8600_IO_Data_submodule)
UDT for buffering input parameters.
Structure of UDT_Data_Buffering_1 data type
Byte Enables or disables buffer mode
(0 = no, any other value = yes)
(0 = no, any other value = yes)
Charge ready threshold (10 to 90 %)
Power interrupt enable (0 = no, any other value = yes)
Power interrupt dead time (0 to 60000 ms)
Power interrupt wait time (0 to 300000 ms)
Power_interrupt_
interrupttime
UInt Power interrupt - interrupt time (0 to 60000 ms)
Pre_charg_buf_comp_bef_
out en
Byte Charge buffer components before output activation
Start_from_battery_start_
out1 only
Byte Switch on only output 1 after start from battery