Siemens SlMATlC S5-010W - Memory Interface; Timing

5. Appendix
5.2 Memory interface
5.3 Timing
5.2 Memory interface
cba
shown on the plug connector of the memory submodule (looking at
1
the pin side)
2
A, to All
Address bus, bit 0 to 11
0,07
Data bus, bit 0 to 7
CS 1, 2
CHIP SELECT. Enabling of firstlsecond EPROM of user
memory
PD
1, 2 Programming input of firstlsecond EPROM ("Read"
enable)
K1 to K5 Identification for memory capacity (0.5K, 1K or 2K
statements)
K6 Battery test pin
VKE Result of logic operation (RLO)
STAT Signal status of
I10 modules
W Block end
RI A Initializing pulse request
fS Stop clock
Text
- External clock
TI Basic clocking of CPU
NOP No
oweration (test module: "1" e NOP)
3- Stop'address 'counter
FP, FR Enable
I10 or RAM
Rio Internal initializing pulse 15
STOP ScanIStop ("l" e Stop)
VPP
Power supply for readout (+ 5 V) and programming
16
(+25 V) of the EPROMs
5.3 Timing
-
T1
: Basic clock of CPU
FP : l10 enable
Fa
: RAM enable
VKE : Result of logic operation (RLO)
IQ
: First scan (IQ)
CL,,,: Clock pulse for RLO
CLEA : Clock pulse for first scan
Fig. 31 Timing