5.3.2
When
the
keyboard
scanning routines
are
entered
the CPU
performs
successive
I/O
read cycles
setting
the
IOREQ
and RD
lines
to the
IJLA,
low. At the same time, the I/O port addresses placed on the upper
half of the address bus are modified with each cycle such that each of
the address lines A15 through A8 is set low in turn, the other lines
remaininghigh.
5.3.3 The seguence starts with I/O port address FE driving address line A8
low.
The
keyboard
matrix
also
sees
this
potential
on
column
6
applied
via D6 and the ribbon cable KB2. Thus, when any of the switches on
the inter-section with column 6 is pressed, the corresponding row
output supplying
the ULA via the
second
ribbon
cable
(KB1),
is
pulled
low. The row signal(s) is subseguently inverted by the ULA and placed
on one of the
five
low
order data
bus
lines.
For
example,
if the
CAPS
SHIFT
key is
pressed
row one
output
drives
data
bus DO
high
and so on.
The seguence ends with I/O address 7F when column 8 is addressed. In
this
instance, operation
of the
SPACE
key
drives
DO
high. Clearly,
the
keyboard
scanning routines
make
the
distinction
between
the
CAPS
SHIFT
and
SPACE
key by
knowing
which
address
line
is
being driven.
5.4 Tape Interface
5.4.1
When LOADing
or
SAVEing
programs
using
a
cassette
recorder,
the ULA
transfers information between the MIC and EAR sockets and the data
bus,
performing
A/D and D/A
conversions
as
reguired. Since
the
LOAD
and
SAVE
functions
are
mutually exclusive,
a
single
pin on the ULA
(i.e. pin 28) is used both for input and output. Separate I/O
read/write cycles to port address 254 configure the pin accordingly.
During
the
LOAD
operation
the CPU
executes successive
I/O
read cycles,
reading
the EAR
input
off
data
bus 6.
When
performing
a
SAVE
operation, the CPU executes successive I/O write cycles, this time
writing data to the MIC output via data bus 3.
5.4.2
To
ensure
that
I/O
cycles
are
correctly
implemented,
the
IOREQ
line
supplying
the ULA is
gated with address
line
AO via
TR6.
Thus,
if any
memory transactions occur where AO is high (i.e. not port address 254)
then
the
IOREQ
input
is
forced
high
inhibiting
any
attempt
to
perform
an I/O cycle.
5.4.3
Loudspeaker
(BEEP)
Operation.
It
should
be
noted
that
while
SAVEing,
the level of the MIC output is barely sufficient to drive the
loudspeaker via D9 and TR7 (D10). However, during the execution of a
BEEP
instruction
the CPU
writes instead
to
port
254 on
data
bus 4.
This effectively boosts the MIC output, driving the loudspeaker so
that
the
BEEP
tone
can be
easily
heard.
During
the
execution
of
such
an instruction the cassette recorder is not running so there is no
conflict
at the
MIC/EAR
sockets.
1.10
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