3. Z80A CPU
3.1 The
Z80A
is an
8-bit
single-IC
central
processing
unit
(CPU).
It is
clocked
at
14.0
MHz
from
an
external source controlled
by the
logic
gate array (ULA) and has a standard three bus input/output
arrangement. These buses are the Data Bus, Address Bus and Control
Bus respectively.
3.2
Data
Bus.
D7-D10
constitutes
an
8-bit
bi-directional
data
bus
with
active
high,
tri-state
input/outputs.
It is
used
for
data
exchanges
with the memory and with the ULA.
3.3
Address
Bus.
A15-AO
constitutes
a
16-bit
address
bus
with
active
high, tri-state outputs. The address bus provides the address for
memory (up to 64k bytes) data exchanges and for data exchanges with
the ULA. It is also used during the interrupt routine (see below)
when scanning the keyboard matrix.
3.4 Control Bus. The control bus is a collection of individual signals
which generally organise the flow of data on the address and data
buses. The block diagram only shows five of these signals although
others of minor importance are made available at the expansion port
(see Figures 1.4 and 1.5 for details).
3.5
Starting
with
memory
reguest
fMREQ),
this
signal
is
active
low
indicating
when
the
address
bus
holds
a
valid
address
for a
memory
read
or
memory
write operation. Input/Output reguest
(IORQ)
is
also
active
low but
indicates
when
the
lower half
of the
address
bus
holds
a valid I/O address for the ULA during I/O read/write operations.
3.6 The read and write signals (RD and WR) are active low, and one or
other is active indicating that the CPU wants to read or write data to
a
memory
location
or I/O
device.
All the
control
signals
discussed
so
far are active low, tri-state outputs.
The control signal described here is the interrupt
3.7
last
maskable
(INT).
This
input
is
active
low and is
generated
by the ULA
once
every 20 ms. Each time it is received the CPU 'calls' the 'maskable
interrupt' routine during which the real-time is incremented and the
keyboard is scanned.
3.8 CPU
Clock. Returning
to the CPU
clock
mentioned
earlier
in
this
section, the ULA is able to inhibit this input bringing the CPU to a
temporary
halt.
This
mechanism
gives
the ULA
absolute
priority,
allowing it to access the standard 16k RAM without interference from
the CPU (see RAM description). Switching transistor TR3 ensures that
the clock amplitude is +5V rather than some arbitrary TTL level. This
is essential if the CPU is to operate effectively while executing fast
machine code programs of the 'space invader' ^'
1.2
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