3.9
Dynamic
Memory
Refresh.
The CPU
incorporates
built-in
dynamic
RAM
refresh circuitry. As part of the instruction OP code fetch cycle,
the CPU
performs
a
memory
request after
first
placing
the
refresh
address on the lower eight bits of the address bus. At the end of the
cycle the address is incremented so that over 255 fetch cycles, each
row of the dynamic RAM is refreshed. This mechanism only applies to
the optional 32k expansion RAM in the 48k Spectrum. An alternative
refresh method is adapted for the standard 16K RAM.
4. MEMORY ORGANISATION
4.1 In the
standard
16k
Spectrum
there
are 32k
bytes
of
addressable
memory
equally divided between ROM and RAM.
4.2 The
lower
16k
bytes
of
memory
(addresses
0000
-
3FFF)
are
implemented
in a single ROM (IC5) which holds the monitor program. This program
is a complex Z80 machine code program divided broadly into three parts
one
each covering
the
input/output routines,
the
BASIC
interpreter
and
expression handling. Details of the program content, although outside
the
scope
of
this
manual,
are
referred
to as
necessary.
4.3 The
upper
16
bytes
of
memory
(addresses
4000
-
7FFF)
are
implemented
using
eight
16k bit
dynamic
RAMs
(IC6-IC13).
Approximately half
of
this
space
is
available
to the
user
for
writing
BASIC
or
machine
code
programs. The remainder is used to hold the system variables
including 6k bytes reserved for the memory mapped display area.
4.4 In the 48k Spectrum an additional 32k bytes of RAM are provided
(addresses
8000
-
FFFF)
which
are
implemented using
eight
32k bit
dynamic
RAMs
(IC15-IC32).
The
RAM, providing
extra
memory
space
for
the user, is normally fitted during manufacture but may be added
retrospectively
using
the
RAM
expander
kit.
In
addition
to the
RAMs,
the kit includes the address multiplexer and read/write control ICs
IC23-IC26.
Board
space
and the
necessary
discrete
components
are
already provided on the board.
4.5 Read/Write Operations
4.5.1 The following description should be read in conjunction with the
circuit diagrams given in Figures 1.4 and 1.5.
4.5.2 Read Only Memory (ICS). The CPU addresses the ROM directly during
memory read cycles using the address bus A13-AO. MREQ and RD enable
the ROM and the ROM outputs respectively. A third input (CS) derived
by the ULA 'ROMCS) selects the ROM, provided the higher order address
bits A14 and A15 are both low. These are reserved for accessing the
RAM memory which starts with address 4000 (i.e. address A14 set). An
external ROM 1C select input, supplied via the expansion port on pin
25A, selectively disables the on-board ROM by pulling the select input
high. By virtue of R33 placed on the ULA side of the ROM the ULA
ROMCS output is effectively inhibited. Interface 1 uses this
1.4
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