Sony CDX-GT525U - Page 51

CDX-GT52UM/GT470UE/GT470UM/GT472UE/GT472UM/GT474UM/GT520U/GT525U
51
Pin No. Pin Name I/O Description
69 ADVDD3 - Power supply terminal (+3.3V)
70 ADIN1 (IN_L-CH) I Audio signal input terminal (L channel)
71 ADVREFL O Reference voltage output terminal
72 ADVCM O Reference voltage output terminal
73 ADVREFH O Reference voltage output terminal
74 ADIN2 (IN_R-CH) I Audio signal input terminal (R channel)
75 ADVSS3 - Ground terminal
76 MS I I/F mode selection signal input terminal Fixed at “L” in this unit
77 to 80
CD_BUS0 to
CD_BUS3
I Serial data input from the sub system controller
81 CD_BUCK I Serial data transfer clock signal input from the sub system controller
82 CD_XCCE I Chip enable signal input from the sub system controller
83 VDD3-2 - Power supply terminal (+3.3V)
84 VSS-3 - Ground terminal
85 /RST I Reset signal input from the main system controller
86 VDD1-4 - Power supply terminal (+1.5V)
87 DEC_INT O Request signal output to the sub system controller
88 BSIF_INT O Request signal output to the sub system controller
89 BSIF_GATE I Gate signal input from the sub system controller
90 BSIF_DATA I Audio data input from the sub system controller
91 BSIF_BCK I Bit clock signal input from the sub system controller
92 BSIF_LRCK I L/R sampling clock signal (44.1 kHz) input terminal for audio data input
93 DEC_XMUTE I Muting on/off control signal input from the sub system controller
94 ZDET O Zero detection signal output terminal
95 SP_DATA O Spectrum analyzer data output to the sub system controller
96 SP_CLK I Spectrum analyzer data transfer clock signal input from the sub system controller
97 TEST I Setting terminal for test mode Normally fi xed at “L”
98 PDO O Phase error margin signal between EFM signal and PLCK signal output terminal
99 TMAX O TMAX detection result output terminal
100 LPFN I Inverted signal input from the operation amplifi er for PLL loop fi lter