Sony CDX-GT610UG - Page 39

CDX-GT61UMS/GT560UE/GT560UI/GT560US/GT564UI/GT610UG/GT610US/GT616UG
39
Pin No. Pin Name I/O Description
69 ADVDD3 - Power supply terminal (+3.1V)
70 ADIN1 (IN_L-CH) I Audio signal input terminal (L channel)
71 ADVREFL O Reference voltage output terminal
72 ADVCM O Reference voltage output terminal
73 ADVREFH O Reference voltage output terminal
74 ADIN2 (IN_R-CH) I Audio signal input terminal (R channel)
75 ADVSS3 - Ground terminal
76 MS I I/F mode selection signal input terminal Fixed at “L” in this unit
77, 78 BUS0, BUS1 I/O Bus data input/output terminal Not used
79 So O Serial data output to the CD drive/USB controller
80 Si I Serial data input from the CD drive/USB controller
81 SCL I Bus clock signal input from the CD drive/USB controller
82 /CCE I Chip enable signal input from the CD drive/USB controller
83 VDD3-2 - Power supply terminal (+3.1V)
84 VSS-3 - Ground terminal
85 /RST I Reset signal input from the system controller
86 VDD1-4 - Power supply terminal (+1.5V)
87 DEC_REQ O Request signal output to the CD drive/USB controller
88 BSIF-REQ O Request signal output to the CD drive/USB controller
89 BSIF-GATE I Gate signal input from the CD drive/USB controller
90 BSIF_DATA I Audio data input from the CD drive/USB controller
91 BSIF_BCK I Bit clock signal input from the CD drive/USB controller
92 BSIF_LRCK I L/R sampling clock signal (44.1 kHz) input terminal for audio data input
93 BSIF_XMUTE I Muting on/off control signal input from the CD drive/USB controller
94 ZDET O Zero detection signal output terminal
95 SP_DATA O Spectrum analyzer data output to the system controller
96 SP_CLK I Spectrum analyzer data transfer clock signal input from the system controller
97 TEST I Setting terminal for test mode Normally fi xed at “L”
98 PDO O Phase error margin signal between EFM signal and PLCK signal output terminal
99 TMAX O TMAX detection result output terminal\
100 LPFN I Inverted signal input from the operation amplifi er for PLL loop fi lter