RM0046 Flash Memory
Doc ID 16912 Rev 5 319/936
1. Invalid—the buffer contains no valid data.
2. Used—the buffer contains valid data that has been provided to satisfy an AHB burst
type read.
3. Valid—the buffer contains valid data that has been provided to satisfy an AHB single
type read.
4. Prefetched—the buffer contains valid data that has been prefetched to satisfy a
potential future AHB access.
5. Busy AHB—the buffer is currently being used to satisfy an AHB burst read.
6. Busy Fill—the buffer has been allocated to receive data from the Flash array, and the
array access is still in progress.
Selection of a buffer to be loaded on a miss is based on the following replacement algorithm:
1. First, the buffers are examined to determine if there are any invalid buffers. If there are
multiple invalid buffers, the one to be used is selected using a simple numeric priority,
where buffer 0 is selected first, then buffer 1, etc.
2. If there are no invalid buffers, the least-recently-used buffer is selected for replacement.
Once the candidate page buffer has been selected, the Flash array is accessed and read
data loaded into the buffer. If the buffer load was in response to a miss, the just-loaded
buffer is immediately marked as most-recently-used. If the buffer load was in response to a
speculative fetch to the next-sequential line address after a buffer hit, the recently-used
status is not changed. Rather, it is marked as most-recently-used only after a subsequent
buffer hit.
This policy maximizes performance based on reference patterns of Flash accesses and
allows for prefetched data to remain valid when non-prefetch enabled bus masters are
granted Flash access.
Several algorithms are available for prefetch control that trade off performance versus
power. They are defined by the Bx_Py_PFLM (prefetch limit) register field. More aggressive
prefetching increases power slightly due to the number of wasted (discarded) prefetches,
but may increase performance by lowering average read latency.
In order for prefetching to occur, a number of control bits must be enabled. Specifically, the
global buffer enable (Bx_Py_BFE) must be set, the prefetch limit (Bx_Py_PFLM) must be
non-zero and either instruction prefetching (Bx_Py_IPFE) or data prefetching
(Bx_Py_DPFE) enabled. Refer to Section 17.3.6, “Registers description for a description of
these control fields.
Instruction/data prefetch triggering
Prefetch triggering may be enabled for instruction reads via the Bx_Py_IPFE control field,
while prefetching for data reads is enabled via the Bx_Py_DPFE control field. Additionally,
the Bx_Py_PFLIM field must also be set to enable prefetching. Prefetches are never
triggered by write cycles.
Per-master prefetch triggering
Prefetch triggering may be also controlled for individual bus masters. AHB accesses
indicate the requesting master via the hmaster[3:0] inputs. Refer to Section , “Platform Flash
Access Protection Register (PFAPR) for details on these controls.
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