ST SPC560P34 - Figure 397. Hold Register (HOLD); Figure 398. Counter Register (CNTR); Table 369. LOAD Field Descriptions; Table 370. HOLD Field Descriptions

RM0046 eTimer
Doc ID 16912 Rev 5 713/936
Hold register (HOLD)
This read-only register stores the counter’s value whenever any of the other counters within
a module are read. This supports coherent reading of cascaded counters.
Counter register (CNTR)
This read/write register is the counter for this channel of the timer module. This register is
not byte accessible.
Table 369. LOAD field descriptions
Field Description
LOAD[15:0]
Load
Stores the value used to initialize the counter.
This register is not byte accessible.
Figure 397. Hold register (HOLD)
Address:
Base + 0x000A (eTimer0)
Base + 0x002A (eTimer1)
Base + 0x004A (eTimer2)
Base + 0x006A (eTimer3)
Base + 0x008A (eTimer4)
Base + 0x00AA (eTimer5)
Access: User read-only
0123456789101112131415
RHOLD[15:0]
W
Reset0000000000000000
Table 370. HOLD field descriptions
Field Description
HOLD[15:0]
Stores the counter’s value whenever any of the other counters within a module are read.
The hardware request status reflects the state of the request as seen by the arbitration logic. Therefore,
this status is affected by the EDMA_ERQRL[ERQn] bit.
Figure 398. Counter register (CNTR)
Address:
Base + 0x000C (eTimer0)
Base + 0x002C (eTimer1)
Base + 0x004C (eTimer2)
Base + 0x006C (eTimer3)
Base + 0x008C (eTimer4)
Base + 0x00AC (eTimer5)
Access: User read/write
0123456789101112131415
R
CNTR[15:0]
W
Reset0000000000000000