ST SPC560P34 - Figure 471. CRC-CCITT Engine Concept Scheme

Cyclic Redundancy Check (CRC) RM0046
798/936 Doc ID 16912 Rev 5
The data stream is generally executed by N concurrent DMA data transfers (mem2mem)
where N is less or equal to the number of contexts.
Two standard generator polynomials are given in Equation 35 and Equation 36 for the CRC
computation of each context.
Equation 35CRC-16-CCITT (x25 protocol)
Equation 36CRC-32 (ethernet protocol)
Figure 471. CRC-CCITT engine concept scheme
The initial seed value of the CRC can be programmed initializing the CRC_CSTAT register.
The concept scheme (serial data loading) of the CRC engine is given in Figure 471 for the
CRC-CCITT. The design implementation executes the CRC computation in a single clock
cycle (parallel data loading). A pipeline scheme has been adopted to de-couple the IPS bus
interface from the CRC engine in order to allow the computation of the CRC at speed (zero
wait states).
In case of usage of the CRC signature for encapsulation in the data frame of a
communication protocol (e.g., SPI, ..) a bit swap (MSB  LSB, LSB  MSB) and/or bit
inversion of the final CRC signature can be applied (CRC_OUTP register) before to transmit
the CRC.
The usage of the CRC is summarized in the flow-chart given in Figure 472.
X
16
X
12
X
5
1+++
X
32
X
26
X
23
X
22
X
16
X
12
X
11
X
10
X
8
X
7
X
5
X
4
X
2
X1++++++++++++++
Serial
data
input
(LSB first)
+
0
4
5
11
+
15
+
12