ST ST32M103 Series - Page 273

UM0306 General purpose timer (TIMx)
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Bits 9:8
CC4S: Capture/Compare 4 Selection.
This bit-field defines the direction of the channel (input/output) as well as the used
input.
00: CC4 channel is configured as output.
01: CC4 channel is configured as input, IC4 is mapped on TI4.
10: CC4 channel is configured as input, IC4 is mapped on TI3.
11: CC4 channel is configured as input, IC4 is mapped on TRGI. This mode is
working only if an internal trigger input is selected through TS bit (TIMx_SMCR
register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = ’0’ in
TIMx_CCER).
Bits 7:4 IC3F: Input Capture 3 Filter.
Bits 3:2 IC3PSC: Input Capture 3 Prescaler.
Bits 1:0
CC3S: Capture/Compare 3 Selection.
This bit-field defines the direction of the channel (input/output) as well as the used
input.
00: CC3 channel is configured as output.
01: CC3 channel is configured as input, IC3 is mapped on TI3.
10: CC3 channel is configured as input, IC3 is mapped on TI4.
11: CC3 channel is configured as input, IC3 is mapped on TRGI. This mode is
working only if an internal trigger input is selected through TS bit (TIMx_SMCR
register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = ’0’ in
TIMx_CCER).
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