To Next Page

To Previous Page

Ethernet (ETH): media access control (MAC) with DMA controller RM0008

998/1096 Doc ID 13902 Rev 12

● RDES1: Receive descriptor Word1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DIC

RBS2 RBS2

RER

RCH

Reserved

RBS

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 DIC: Disable interrupt on completion

When set, this bit prevents setting the Status register’s RS bit (CSR5[6]) for the received frame

ending in the buffer indicated by this descriptor. This, in turn, disables the assertion of the interrupt to

Host due to RS for that frame.

Bits 30:29 Reserved

Bits 28:16 RBS2: Receive buffer 2 size

These bits indicate the second data buffer size, in bytes. The buffer size must be a multiple of 4, 8,

or 16, depending on the bus widths (32, 64 or 128, respectively), even if the value of RDES3

(buffer2 address pointer) is not aligned to bus width. If the buffer size is not an appropriate multiple of

4, 8 or 16, the resulting behavior is undefined. This field is not valid if RDES1 [14] is set.

Bit 15 RER: Receive end of ring

When set, this bit indicates that the descriptor list reached its final descriptor. The DMA returns to the

base address of the list, creating a descriptor ring.

Bit 14 RCH: Second address chained

When set, this bit indicates that the second address in the descriptor is the next descriptor address

rather than the second buffer address. When this bit is set, RBS2 (RDES1[28:16]) is a “don’t care”

value. RDES1[15] takes precedence over RDES1[14].

Bit 13 Reserved

Bits 12:0 RBS1: Receive buffer 1 size

Indicates the first data buffer size in bytes. The buffer size must be a multiple of 4, 8 or 16,

depending upon the bus widths (32, 64 or 128), even if the value of RDES2 (buffer1 address pointer)

is not aligned. When the buffer size is not a multiple of 4, 8 or 16, the resulting behavior is undefined.

If this field is 0, the DMA ignores this buffer and uses Buffer 2 or next descriptor depending on the

value of RCH (bit 14).

ST STM32F101xx User Manual

Questions and Answers: