Technics SX-KN6500 - Page 92

SCHEMATIC DIAGRAM-14
A0
A1
A2
W
X
Y
A
B
C
D
E
F
G
H
R
S
U
V
T
I
J
K
L
M
N
O
P
Q
W
X
Y
CS2
CS3
CS1
GND
VCC
7
6
5
4
3
2
1
0
21
AD
DT
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
V
U
T
S
R
Q
P
O
N
M
L
K
J
I
H
G
F
E
D
C
B
A
H
G
F
E
D
C
B
A
P
O
N
M
L
K
J
H
G
F
E
D
C
B
A
15
OE
VCC BYTE
VSSVSS
CE
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
44
43
2
3
34
35
36
37
38
39
40
41
42
4
5
6
7
8
9
10
11
31
29
27
25
22
20
18
16
30
28
26
24
21
19
17
15
12
23 33
13 32
14
21
AD
DT
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
V
A
U
T
S
R
Q
P
O
N
M
L
K
J
I
H
G
F
E
D
C
B
A
P
O
N
M
L
K
J
I
G
F
E
D
C
B
A
15
OE
VCC BYTE
VSSVSS
CE
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
44
43
2
3
34
35
36
37
38
39
40
41
42
4
5
6
7
8
9
10
11
31
29
27
25
22
20
18
16
30
28
26
24
21
19
17
15
12
23 33
13 32
14
21
AD
DT
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
V
U
T
S
R
Q
P
O
N
M
L
K
J
I
H
G
F
E
D
C
B
A
P
O
N
M
L
K
J
H
G
F
E
D
C
B
A
15
OE
VCC BYTE
VSSVSS
CE
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
44
43
2
3
34
35
36
37
38
39
40
41
42
4
5
6
7
8
9
10
11
31
29
27
25
22
20
18
16
30
28
26
24
21
19
17
15
12
23 33
13 32
14
21
AD
DT
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
V
U
T
S
R
Q
P
O
N
M
L
K
J
I
H
G
F
E
D
C
B
A
P
O
N
M
L
K
J
I
G
F
E
D
C
B
A
15
OE
VCC BYTE
VSSVSS
CE
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
44
43
2
3
34
35
36
37
38
39
40
41
42
4
5
6
7
8
9
10
11
31
29
27
25
22
20
18
16
30
28
26
24
21
19
17
15
12
23 33
13 32
14
7
9
10
11
12
13
14
15
1
2
3
4
5
6
16
8
C224
0.1
C222
0.1
C225
0.1
C223
0.1
R210
100
C221
0.1
+3.3D
C220
0.1
+3.3D
A0
A1
A2
W
X
Y
CS1
GND
VCC
7
6
5
4
3
2
1
0
H
G
F
E
D
C
B
A
7
9
10
11
12
13
14
15
1
2
3
4
5
6
16
8
A B
B
JP201
+5D
GND VCC
1 2 3 4 5
TC7SZ32FU
(2 INPUT OR GATE)
IC215
+3.3D
Y
Y
HH
II
TC74VHC138F
(3 TO 8 DECODER)
IC204
TC74VHC138F
(3 TO 8 DECODER)
IC203
QSIGX3C64004
(64M BIT MASK ROM)
IC205
QSIGX3C64005
(64M BIT MASK ROM)
IC206
QSIGX3C64007
(64M BIT MASK ROM)
IC208
QSIGX3C64006
(64M BIT MASK ROM)
IC207
CS2
CS3