Texas Instruments 99/4A - Page 120

LS19A
A BIT BI-DIRECTIONAL SHIFT REGISTER
POSITIVE EDGE TRIGGERING (T )
A MODES OF OPERATION: (A) PARALLEL LOAD
(B) SHIFT RIGHT (QA TO QD)
(C) SHIFT LEFT (QD TO QA)
(D) INHIBIT CLOCK (DO NOTHING)
Parallel Inputs and Outputs
Four Operating Modes:
Synchronous Parallel Load
Right Shift
Left Shift
Do Nothing
• Positive Edge-Triggered Clocking
• Direct Overriding Clear
TYPE
TYPICAL
MAXIMUM
CLOCK
FREQUENCY
TYPICAL
POWER
DISSIPATION
•194
36 MH 2
195 mW
LS194A
36 MH x
75 mW
‘ SI 94
105 MHf
425 mW
description
SN741M. SN74LS194A. SN74S1M ... J OR N PACKAGE
These bioirectional shift registers are designed to incorporate virtually ail of the features a system designer may want m
a shift register. The circuit contains 46 equivalent gates and features parallel inputs, parallel outputs, right-shift and
left shift serial inputs, operating-mode-control inputs, and a direct overriding clear line. The register has four distinct
modes of operation, namely:
Parallel (broadside) load
Shift right (in the direction Q a toward Q q )
Shift left (in the direction Q q toward Q a )
Inhibit clock (do nothing)
Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, SO
and SI. high. The data are loaded into the associated flip-flops and appear at the outputs after the positive transition
of the clock input. During loading, serial data flow is inhibited.
Shift right is accomplished synchronously with the rising edge of the dock pulse when SO is high and SI is low. Serial
data for this mode is entered at the shift-right data input. When SO is low and S1 is high, data shifts left synchronously
and new data is entered at the shift-left serial input.
Clocking of the flip-flop i$ inhibited when both mode control inputs
SN54194/SN74194 should be changed only while the clock input is high.
are low. The mode controls cf the
FUNCTION TABLE
INPUTS
OUTPUTS
H • high level (steedv State)
 CAD
MODE
/* 1 o/* w
SERIAL I
!
PARA
U “ low level ( steed V State!
CLt AH
SI
SO
LLULK
LEFT RIGHT A
B
c r
0
Q a
q b
°C Qo
X ■ irrelevant (any moot. including tran
L
X X X
X
X
X X
X
X
L L
L
L
’ • transition from low to nigh i « v « i
H
H
X
L
X
H
H
L
T
X
X
X
X
H
X
a
X
X
b
X
X
c
X
X
d
X
Q ao
a
H
Q bo
0
Q aa
Q co
c
Q0n
Qoo
d
Qcn
a. h. c. d - tna level ot steed vst ate <npui at
moots A. 0 C, or O respectively
Q AO- q BO- Q CO- q OO “ °* q a
Qg. Q^. or Q q . rtio«bv«iy oelore me
H
L
H
?
X
L
X
X X
X
L
□An
Qen Qcn
indicated steadvstate mout cono itions
H
H
H
H
L
L
r
H
1.
X
X
X
X
X
X
X
X
X
X
Qgn
Ofin
Q Cn
Qcn
Qon
□on
H
D
>
0
?
J
®
D
t
'
®
•
0
?
e
°
0
5
1
0
0
l o l I I
Q a
most
H
L
L
X
1 x
X
X
X X X
Q ao
Q eo Q co
Q oo
recent ’ transition o» the clock
Fig. 32
RAG 06-03-82
111