Texas Instruments 99/4A - Page 73

I DEO DISPLAY PROCESSOR
ENERAL DESCRIPTION
The TNS SRls video display processor is capable of generatina a
complete NTSC color television video signal. The information to
be displayed is stored in dynamic RAM, with the TMS 9918 genera —
ting all the necessary interfacing signals.
The VDP will generate a solid color border and background on which
a 32 X 24 matrix of 8X3 picture element patterns is superim 
posed. In addition a high degree of mobility and resolution is
provided in the form of the sprites, or dynamic patterns, which
are further superimposed on the pattern display.
An option can be selected whereby the VDP can function as a 40X24
character alphanumeric terminal by setting the text command bit to
one .
ARCHITECTURE
Figure. 29, p.71 shows the block diagram of the video display pro 
cessor. Interface to the CPU is via an 8 bit bidirectional port
controlled by two select and one address lines. Interface to the
refresh RAM is via an 8 bit data bus,
and 3 control lines. The VDP provides
signals to the system via the GROM
and CPU INT signal lines.
an 8 bit address/data bus,
clock and synchronization
CLP, CPU, CLP, 'and CPU INT
Interface to the
video output signal
target
televi si on
is provided by a composite
OSCILLATOR AND CLOCK GENERATION
The video display system is designed to operate with a 10.738635
MHz + /- 50 PPM crystal input to generate the required internal
clock signals. A fundamental frequency parallel mode crystal is
used as the frequency reference for the internal clock oscillator,
which is the master time base for all system operation. This
master clock is divided by 2 to generate the dot clock rate of 5.3
MHz. The master clock is divided by 3 to provide the CPU clock.
The GROM clock is developed from the master clock divided by 24.
additionally, the master clock and its compliment are divided by 3
in 2 stages to provide the 6 basic color phase fre- quencies which
generate the color to the target color TV.
COLOR PHASE GENERATION
The 10.7 + MHz master clock and its compliment are used to generate
a 6 phase 3.57545 MHz (+/-10Hz) clock to provide the video color
signals and the color burst reference for use in developing the
composite video output signal. Table 11 shows the six colors, the'
standard phase shifts, and the color approximations provided by-
the VDP. While the VDP signals are not exact equivalencies, the
differences can easily be adjusted by the color and tint control
of the target color television. To insure compatibi 1 itv with
monochrome television receivers, an intensity level on the gray
scale is assigned to each color signal.