Texas Instruments AFE79 Series - 2.3.32 Register 46 h (offset = 46 h) [reset = FAh]

www.ti.com JESD_SUBCHIP Register Map
179
SBAU337–May 2020
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
Serial Interface Register Maps
Table 2-75. Register 45 Field Descriptions
Bit Field Type Reset Description
7-6
MUX_SEL_FBCD_
Q1_FOR_2R1F_A
B
R/W 3h
TO CONTROL DATA GOING TO 2R1F_AB i.e.
STX1,STX2,STX3,STX4 (assuming no lane-mux)
Selects the ddc stream that is to be routed to jesd 2R1F
instance0 fbcd_3
0 : fbab_q_s0
1 : fbab_q_s1
2 : fbcd_q_s0
3 : fbcd_q_s1
Using LATTE to configure this register is recommended.
5-4
MUX_SEL_FBCD_I
1_FOR_2R1F_AB
R/W 3h
TO CONTROL DATA GOING TO 2R1F_AB i.e.
STX1,STX2,STX3,STX4 (assuming no lane-mux)
Selects the ddc stream that is to be routed to jesd 2R1F
instance0 fbcd_2
0 : fbab_i_s0
1 : fbab_i_s1
2 : fbcd_i_s0
3 : fbcd_i_s1
Using LATTE to configure this register is recommended.
3-2
MUX_SEL_FBCD_
Q0_FOR_2R1F_A
B
R/W 2h
TO CONTROL DATA GOING TO 2R1F_AB i.e.
STX1,STX2,STX3,STX4 (assuming no lane-mux)
Selects the ddc stream that is to be routed to jesd 2R1F
instance0 fbcd_1
0 : fbab_q_s0
1 : fbab_q_s1
2 : fbcd_q_s0
3 : fbcd_q_s1
Using LATTE to configure this register is recommended.
1-0
MUX_SEL_FBCD_I
0_FOR_2R1F_AB
R/W 2h
TO CONTROL DATA GOING TO 2R1F_AB i.e.
STX1,STX2,STX3,STX4 (assuming no lane-mux)
Selects the ddc stream that is to be routed to jesd 2R1F
instance0 fbcd_0
0 : fbab_i_s0
1 : fbab_i_s1
2 : fbcd_i_s0
3 : fbcd_i_s1
Using LATTE to configure this register is recommended.
2.3.32 Register 46h (offset = 46h) [reset = FAh]
Figure 2-73. Register 46h
7 6 5 4 3 2 1 0
MUX_SEL_FBAB_Q1_FOR_2R1
F_CD
MUX_SEL_FBAB_I1_FOR_2R1F
_CD
MUX_SEL_FBAB_Q0_FOR_2R1
F_CD
MUX_SEL_FBAB_I0_FOR_2R1F
_CD
R/W-3h R/W-3h R/W-2h R/W-2h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-76. Register 46 Field Descriptions
Bit Field Type Reset Description
7-6
MUX_SEL_FBAB_
Q1_FOR_2R1F_C
D
R/W 3h
TO CONTROL DATA GOING TO 2R1F_CD i.e.
STX5,STX6,STX7,STX8 (assuming no lane-mux)
Selects the ddc stream that is to be routed to jesd 2R1F
instance1 fbab_3
0 : fbcd_q_s0
1 : fbcd_q_s1
2 : fbab_q_s0
3 : fbab_q_s1
Using LATTE to configure this register is recommended.