Texas Instruments AFE79 Series - 2.3.40 Register 4 Eh (offset = 4 Eh) [reset = 54 h]; 2.3.41 Register 4 Fh (offset = 4 Fh) [reset = 76 h]

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SBAU337–May 2020
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Serial Interface Register Maps
Table 2-83. Register 4D Field Descriptions
Bit Field Type Reset Description
6-4
TXOCTETPATH3_
CLK_SEL
R/W 3h
Selects the input SERDES-Tx lane clk for data that is normally
supposed to be on STX4.
0 : sel lane0 clk
1 : sel lane1 clk
2 : sel lane2 clk
3 : sel lane3 clk
4 : sel lane4 clk
5 : sel lane5 clk
6 : sel lane6 clk
7 : sel lane7 clk
2-0
TXOCTETPATH2_
CLK_SEL
R/W 2h
Selects the input SERDES-Tx lane clk for data that is normally
supposed to be on STX3.
0 : sel lane0 clk
1 : sel lane1 clk
2 : sel lane2 clk
3 : sel lane3 clk
4 : sel lane4 clk
5 : sel lane5 clk
6 : sel lane6 clk
7 : sel lane7 clk
2.3.40 Register 4Eh (offset = 4Eh) [reset = 54h]
Figure 2-81. Register 4Eh
7 6 5 4 3 2 1 0
TXOCTETPATH5_CLK_SEL TXOCTETPATH4_CLK_SEL
R/W-5h R/W-4h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 2-84. Register 4E Field Descriptions
Bit Field Type Reset Description
6-4
TXOCTETPATH5_
CLK_SEL
R/W 5h
Selects the input SERDES-Tx lane clk for data that is normally
supposed to be on STX6.
0 : sel lane0 clk
1 : sel lane1 clk
2 : sel lane2 clk
3 : sel lane3 clk
4 : sel lane4 clk
5 : sel lane5 clk
6 : sel lane6 clk
7 : sel lane7 clk
2-0
TXOCTETPATH4_
CLK_SEL
R/W 4h
Selects the input SERDES-Tx lane clk for data that is normally
supposed to be on STX5.
0 : sel lane0 clk
1 : sel lane1 clk
2 : sel lane2 clk
3 : sel lane3 clk
4 : sel lane4 clk
5 : sel lane5 clk
6 : sel lane6 clk
7 : sel lane7 clk
2.3.41 Register 4Fh (offset = 4Fh) [reset = 76h]
Figure 2-82. Register 4Fh
7 6 5 4 3 2 1 0
TXOCTETPATH7_CLK_SEL TXOCTETPATH6_CLK_SEL
R/W-7h R/W-6h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset