LDDW Load Doubleword From Memory With an Unsigned Constant Offset or Register Offset
3-130 Instruction Set SPRU733
Delay Slots 4
Functional Unit
Latency
1
See Also LDB, LDH, LDW
Example 1
LDDW .D2 *+B10[1],A1:A0
Before instruction 5 cycles after instruction
A1:A0
xxxx xxxxh
xxxx xxxxh A1:A0 4021 3333h 3333 3333h
B10 0000 0010h 16 B10 0000 0010h 16
mem 18h 3333 3333h 4021 3333h 8.6 mem 18h 3333 3333h 4021 3333h 8.6
Little-endian mode
Example 2 LDDW .D1 *++A10[1],A1:A0
Before instruction 1 cycle after instruction
A1:A0
xxxx xxxxh
xxxx xxxxh A1:A0 xxxx xxxxh xxxx xxxxh
A10 0000 0010h 16 A10 0000 0018h 24
mem 18h 4021 3333h 3333 3333h
8.6
mem 18h 4021 3333h
3333 3333h 8.6
5 cycles after instruction
A1:A0
4021 3333h
3333 3333h
A10 0000 0018h 24
mem 18h 4021 3333h
3333 3333h 8.6
Big-endian mode
To Next Page
Loading...
