Texas Instruments TMS320C67X - Page 302

STH Store Halfword to Memory With a 5-Bit Unsigned Constant Offset or Register Offset
3-242 Instruction Set SPRU733
Example 2 STH .D1 A1,*A10−−[A11]
Before
instruction
1 cycle after
instruction
3 cycles after
instruction
A1
9A32 2634h
A1 9A32 2634h A1 9A32 2634h
A10 0000 0100h A10 0000 00F8h A10 0000 00F8h
A11 0000 0004h A11 0000 0004h A11 0000 0004h
mem F8h 0000h mem F8h 0000h mem F8h 0000h
mem 100h 0000 mem 100h 0000h mem 100h 2634h