Texas Instruments TMS320C67X - Page 329

Subtract Two 16-Bit Integers on Upper and Lower Register Halves SUB2
3-269 Instruction SetSPRU733
Execution if (cond) {
(lsb16(src1) − lsb16(src2)) → lsb16(dst);
(msb16(src1) − msb16(src2)) → msb16(dst);
}
else nop
Pipeline
Stage
E1
Read src1, src2
Written dst
Unit in use
.S
Instruction Type Single-cycle
Delay Slots 0
See Also ADD2, SSUB, SUB, SUBC, SUBU
Example 1
SUB2 .S1 A3, A4, A5
Before instruction 1 cycle after instruction
A3
1105 6E30h
4357 28208 A3 1105 6E30h 4357 28208
A4 1105 6980h 4357 27008 A4 1105 6980h 4357 27008
A5 xxxx xxxxh A5 0000 04B0h 0 1200
Example 2 SUB2 .S2X B1,A0,B2
Before instruction 1 cycle after instruction
A0
0021 3271h
†
33 12913
‡
A0 0021 3271h
B1 003A 1B48h
†
58 6984
‡
B1 003A 1B48h
B2 xxxx xxxxh B2 0019 E8D7h 25
†
−5929
‡
†
Signed 16-MSB integer
‡
Signed 16-LSB integer
Pipeline