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Texas Instruments TMS320C67X - Page 374

Texas Instruments TMS320C67X
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Functional Unit Constraints
Pipeline4-42 SPRU733
Table 4−26 shows the instruction constraints for MPYI instructions executing
on the .M unit.
Table 4−26. MPYI .M-Unit Instruction Constraints
Instruction Execution
Cycle 1 2 3 4 5 6 7 8 9 10
MPYI R R R R W
Instruction Type
Subsequent Same-Unit Instruction Executable
16 × 16 multiply Xr Xr Xr Xw
4-cycle Xr Xr Xr Xu Xw Xu 
MPYI
Xr Xr Xr 
MPYID
Xr Xr Xr 
MPYDP
Xr Xr Xr Xu Xu Xu 
MPYSPDP
Xr Xr Xr Xu Xu Xu 
MPYSP2DP
Xr Xr Xr Xw Xw Xu 
Instruction Type
Same Side, Different Unit, Both Using Cross Path Executable
Single-cycle Xr Xr Xr
Load 
Store

DP compare
Xr Xr Xr 
2-cycle DP
Xr Xr Xr 
Branch
Xr Xr Xr 
4-cycle
Xr Xr Xr 
INTDP
Xr Xr Xr 
ADDDP/SUBDP
Xr Xr Xr
Legend: = E1 phase of the single-cycle instruction; R = Sources read for the instruction; W = Destinations written for the
instruction;
= Next instruction can enter E1 during cycle; Xr = Next instruction cannot enter E1 during cycle−read/
decode constraint; Xw = Next instruction cannot enter E1 during cycle−write constraint; Xu = Next instruction cannot
enter E1 during cycle−other resource conflict