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Texas Instruments TMS320C67X - Page 379

Texas Instruments TMS320C67X
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Functional Unit Constraints
4-47PipelineSPRU733
Table 4−31 shows the instruction constraints for MPYSP2DP instructions
executing on the .M unit.
Table 4−31. MPYSP2DP .M-Unit Instruction Constraints
Instruction Execution
Cycle 1 2 3 4 5
MPYSP2DP R R W W
Instruction Type
Subsequent Same-Unit Instruction Executable
16 × 16 multiply Xw Xw
MPYDP
Xu 
MPYI
Xu 
MPYID
Xu 
MPYSP
Xw 
MPYSPDP
Xu 
MPYSP2DP
Xw 
Instruction Type
Same Side, Different Unit, Both Using Cross Path Executable
Single-cycle Xr
Load Xr 
Store
Xr 
DP compare
Xr 
2-cycle DP
Xr 
Branch
Xr 
4-cycle
Xr 
INTDP
Xr 
ADDDP/SUBDP
Xr
Legend: = E1 phase of the single-cycle instruction; R = Sources read for the instruction; W = Destinations written for the
instruction;
= Next instruction can enter E1 during cycle; Xr = Next instruction cannot enter E1 during cycle−read/
decode constraint; Xw = Next instruction cannot enter E1 during cycle−write constraint; Xu = Next instruction cannot
enter E1 during cycle−other resource conflict