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Texas Instruments TMS320C67X - Page 387

Texas Instruments TMS320C67X
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Functional Unit Constraints
4-55PipelineSPRU733
Table 4−39 shows the instruction constraints for LDDW instructions executing
on the .D unit.
Table 4−39. LDDW Instruction With Long Write Instruction Constraints
Instruction Execution
Cycle 1 2 3 4 5 6
LDDW RW W
Instruction Type Subsequent Same-Unit Instruction Executable
Instruction with long result Xw
Legend: = E1 phase of the single-cycle instruction; R = Sources read for the instruction; W = Destinations written for the
instruction;
= Next instruction can enter E1 during cycle; Xw = Next instruction cannot enter E1 during cycle-write
constraint