Programming Considerations
Interrupts5-24 SPRU733
Example 5−13 shows a C-based interrupt handler that allows nested
interrupts. The steps are similar, although the compiler takes care of allocating
the stack and saving CPU registers. For more information on using C to access
control registers and write interrupt handlers, see the TMS320C6000
Optimizing C Compiler Users Guide, SPRU187.
Example 5−12. Assembly Interrupt Service Routine That Allows Nested Interrupts
_isr:
STW B0, *B15−−[4] ; Save B0, allocate 4 words of stack
STW B1, *B15[1] ; Save B1 on stack
MVC IRP, B0
STW B0, *B15[2] ; Save IRP on stack
MVC CSR, B0
STW B0, *B15[3] ; Save CSR (and thus PGIE) on stack
OR B0, 1, B1
MVC B1, CSR ; Enable interrupts
; Interrupt service code goes here.
; Interrupts may occur while this code executes.
MVC CSR, B0 ;\
AND B0, −2, B1 ; |−− Disable interrupts.
MVC B1, CSR ;/ (Set GIE to 0)
LDW *B15[3], B0 ; get saved value of CSR into B0
NOP 4 ; wait for LDW *B15[3] to finish
MVC B0, CSR ; Restore PGIE
LDW *B15[2], B0 ; get saved value of IRP into B1
NOP 4
MVC B0, IRP ; Restore IRP
B IRP ; Return from interrupt
|| LDW *B15[1], B1 ; Restore B1
LDW *++B15[4], B0 ; Restore B0, release stack.
NOP 4 ; wait for B IRP and LDW to complete.
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