Control Register File Extensions
2-29CPU Data Paths and ControlSPRU733
Table 2−15. Floating-Point Auxiliary Configuration Register (FAUCR)
Field Descriptions (Continued)
Bit DescriptionValueField
17 NAN2 NaN select for .S2 src2.
0 src2 is not NaN.
1 src2 is NaN.
16
NAN1 NaN select for .S2 src1.
0 src1 is not NaN.
1 src1 is NaN.
15−11
Reserved 0 Reserved. The reserved bit location is always read as 0. A value written to this
field has no effect.
10 DIV0 Source to reciprocal operation for .S1.
0 0 is not source to reciprocal operation.
1 0 is source to reciprocal operation.
9
UNORD Source to a compare operation for .S1
0 NaN is not a source to a compare operation.
1 NaN is a source to a compare operation.
8
UND Result underflow status for .S1.
0 Result does not underflow.
1 Result underflows.
7
INEX Inexact results status for .S1.
0
1 Result differs from what would have been computed had the exponent range
and precision been unbounded; never set with INVAL.
6
OVER Result overflow status for .S1.
0 Result does not overflow.
1 Result overflows.
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