Delay Slots
3-15Instruction SetSPRU733
Table 3−8. Delay Slot and Functional Unit Latency
Instruction Type
Delay
Slots
Functional
Unit Latency
Read Cycles
†
Write
Cycles
†
Single cycle 0 1 i i
2-cycle DP 1 1 i i, i + 1
DP compare 1 2 i, i + 1 1 + 1
4-cycle 3 1 i i + 3
INTDP 4 1 i i + 3, i + 4
Load 4 1 i i, i + 4
‡
MPYSP2DP 4 2 i i + 3, i + 4
ADDDP/SUBDP 6 2 i, i + 1 i + 5, i + 6
MPYSPDP 6 3 i, i + 1 i + 5, i + 6
MPYI 8 4 i, i + 1, 1 + 2, i + 3 i + 8
MPYID 9 4 i, i + 1, 1 + 2, i + 3 i + 8, i + 9
MPYDP
9 4 i, i + 1, 1 + 2, i + 3 i + 8, i + 9
†
Cycle i is in the E1 pipeline phase.
‡
A write on cycle i + 4 uses a separate write port from other .D unit instructions.
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