Texas Instruments TMS320C67X - Page 77

Parallel Operations
3-17Instruction SetSPRU733
Example 3−1. Fully Serial p-Bit Pattern in a Fetch Packet
This p-bit pattern:
00000000
Instruction
A
Instruction
B
Instruction
C
Instruction
D
Instruction
E
Instruction
F
Instruction
G
Instruction
H
31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0
results in this execution sequence:
Cycle/Execute
Packet
Instructions
1 A
2B
3C
4D
5E
6F
7G
8 H
The eight instructions are executed sequentially.
Example 3−2. Fully Parallel p-Bit Pattern in a Fetch Packet
This p-bit pattern:
11111110
Instruction
A
Instruction
B
Instruction
C
Instruction
D
Instruction
E
Instruction
F
Instruction
G
Instruction
H
31 0 31 0 31 0 31 0
31 0 31 0 31 0 31 0
results in this execution sequence:
Cycle/Execute
Packet
Instructions
1 A B C D E F G H
All eight instructions are executed in parallel.