Texas Instruments TMS320C67X - Page 93

Addressing Modes
3-33Instruction SetSPRU733
Table 3−10. Indirect Address Generation for Load/Store
Addressing Type
No Modification of
Address Register
Preincrement or
Predecrement of
Address Register
Postincrement or
Postdecrement of
Address Register
Register indirect *R *++R
*− −R
*R++
*R− −
Register relative *+R[ucst5]
*−R[ucst5]
*++R[ucst5]
*− −R[ucst5]
*R++[ucst5]
*R− −[ucst5]
Register relative with
15-bit constant offset
*+B14/B15[ucst15] not supported not supported
Base + index
*+R[offsetR]
*−R[offsetR]
*++R[offsetR]
*− −R[offsetR]
*R++[offsetR]
*R− −[offsetR]
Table 3−11. Address Generator Options for Load/Store
Mode Field Syntax Modification Performed
0 0 0 0 *−R[ucst5] Negative offset
0 0 0 1 *+R[ucst5] Positive offset
0100 *−R[offsetR] Negative offset
0 1 0 1 *+R[offsetR] Positive offset
1000 *− −R[ucst5] Predecrement
1 0 0 1 *++R[ucst5] Preincrement
1010 *R− −[ucst5] Postdecrement
1 0 1 1 *R++[ucst5] Postincrement
1100 *−−R[offsetR] Predecrement
1 1 0 1 *++R[offsetR] Preincrement
1110 *R− −[offsetR] Postdecrement
1
1 1 1 *R++[offsetR] Postincrement