Toshiba GR200 Series - Page 1087

6F2S1914 (0.49)
GRL200 (Soft 033 & 037)
- 1064 -
Figure 5.4-5 shows the binary output circuits on the BO1A module in order to help
understand the settings. The BO1A consists of 18 binary output circuits and every circuit has
timers and switches. The features of the CPLs are divided into the five components as listed
below:
CPL switch
Selection of input signals
Logic gate switch
Delayed pick-up/delayed drop-off
Logic level inversion
Logic timer switch
BO1
Input signal 1
[LOGIC-SW]
1
&
[BO1_CPL]
Off
On
&
Input signal 2
Input signal 3
Input signal 8
AND
OR
XOR
&
1
1
DRIVER
8002001112
8002001113
Contact
BO1
Reset signal
BO1-SOURCE
310200E11D
From relay
application and
control functions
To external
devices
0
t
Logic Timer
&
Off
Dwell
Latch
Delay
&
0.000-300.000s
&
1
F/F
&
1
1
[INVERSE-SW]
t
0
0.000-300.000s
On Delay Timer
0
t
0.000-300.000s
Off Delay Timer
[TIMER-SW]
&
&
Inverse
Normal
BO2
Input signal 1
[LOGIC-SW]
1
&
[BO2_CPL]
Off
On
&
Input signal 2
Input signal 3
Input signal 8
AND
OR
XOR
&
1
1
DRIVER
810201112
810201113
BO2 RB
BO2
Reset signal
BO2-SOURCE
310201E11D
Contact
0
t
Logic Timer
&
Off
Dwell
Latch
Delay
&
0.000-300.000s
&
1
F/F
&
1
1
[INVERSE-SW]
t
0
0.000-300.000s
On Delay Timer
0
t
0.000-300.000s
Off Delay Timer
[TIMER-SW]
&
&
Inverse
Normal
BO3
Input signal 1
[LOGIC-SW]
1
&
[BO3_CPL]
Off
On
&
Input signal 2
Input signal 3
Input signal 8
AND
OR
XOR
&
1
1
DRIVER
820202112
8202021113
BO3 RB
BO3
Reset signal
BO3-SOURCE
310202E11D
Contact
0
t
Logic Timer
&
Off
Dwell
Latch
Delay
&
0.000-300.000s
&
1
F/F
&
1
1
[INVERSE-SW]
t
0
0.000-300.000s
On Delay Timer
0
t
0.000-300.000s
Off Delay Timer
[TIMER-SW]
&
&
Inverse
Normal
BOn
Input signal 1
[LOGIC-SW]
1
&
[BOn_CPL]
Off
On
&
Input signal 2
Input signal 3
Input signal 8
AND
OR
XOR
&
1
1
DRIVER
8*********
8*********
BOn RB
BOn
Reset signal
BOn-SOURCE
3102E**11D
Contact
0
t
Logic Timer
&
Off
Dwell
Latch
Delay
&
0.000-300.000s
&
1
F/F
&
1
1
[INVERSE-SW]
t
0
0.000-300.000s
On Delay Timer
0
t
0.000-300.000s
Off Delay Timer
[TIMER-SW]
&
&
Inverse
Normal
Figure 5.4-5 Binary Output Circuit for the BO1A (#1 to #n=18)
In Figure 5.4-5 respective element IDs (i.e., 8002001112 and others) designate respective