Toshiba GR200 Series - Page 1399

6F2S1914 (0.49)
GRL200 (Soft 033 & 037)
- 1376 -
The signals are configured with the PLC function, as shown in Figure 11.3-30. The PLC can be
segmented into A to E blocks:
 A Judgements of validities coming from automatic supervision functions
 B Collection and exclusion logics of the judgements results
 C Generator logic of U16_00 quality bits
 D Generator logic of U16_01 quality bits
 E Test bit generator.
The Figure 11.3-30 logics are summarized into ○
1
to ○
20
.
 ○
1
an monitoring result of an automatic supervision function
 ○
2
an error level set by each automatic supervision function
 ○
3
Detection of the absence of an error level which is set
 ○
4
Judgement if Serious error or Serious error(Comm) is occurring
 ○
5
Judgement of Invalid state
 ○
6
Judgement for state of Questionable
 ○
7
Data type conversion
 ○
8
Collection and combination of Invalid states
 ○
9
Collection and combination of Questionable states
 ○
10
Exclusion of Invalid and Questionable state (i.e. priority of Invalid)
 ○
11
14-bit shift operation of Invalid bit in the left direction
 ○
12
15-bit shift operation of questionable bit in the left direction
 ○
13
9-bit shift operation of badReference bit in the left direction
 ○
14
11-bit shift operation of failure bit in the left direction
 ○
15
To align data bits
 ○
16
Collection of Serious error signal
 ○
17
Collection of Minor error signal
 ○
18
Collection of Test mode signal
 ○
19
6-bit shift operation of inaccurate bit in the left direction
 ○
20
4-bit shift operation of test bit in the left direction