Toshiba GR200 Series - Page 232

6F2S1914 (0.49)
GRL200 (Soft 033 & 037)
- 209 -
DEFCR
-CX
1
From EF (EF1)
DEFCF
-CX
OCD-AT
-CX
OCT-BT
-CX
OCT-C
-CX
From PROT-COMMON
S
R
S
R
S
R
≥1
≥1
800000EBBB EFF PHSEL-A
800000EBBC EFF PHSEL-B
800000EBBD EFF PHSEL-C
≥1
1
≥1
≥1
≥1
&
&
&
&
&
&
t 0
TDEFCF
t 0
t 0
0.00 to 0.30s
≥1
≥1
DEFCF-AX
DEFCF-BX
DEFCF-CX
8000001B64
8100001B65
8200001B66
8300001B67
≥1
DEFCR-X
DEFCF-X
t 0
TDEFCB
0.00 to 0.30s
&
From EF (EF2)
To CRL
VTF_DETECT
CB_LOSS_PHASE
From VTF
From PROT COMMON
1
8400001B68
Figure 2.13-8 OCD circuit for BOP
DEFCAR-ARCBlk
8000001B6A
8100001B6B
8200001B6C
≥1
≥1
≥1
≥1
8000001B74
8100001B75
8200001B76
DEFCAR-OPT-A
DEFCAR-OPT-B
DEFCAR-OPT-C
≥1
≥1
≥1
&
≥1
DEFCAR-ARC-BLOCK
8000001B20
8100001B21
8200001B22
DEFCAR-TRIP-A
DEFCAR-TRIP-B
DEFCAR-TRIP-C
≥1
3P
DEFCAR_TPMD
&
8100001B77
Block
Week infeed
trip logic
To TRC
1P
t 0
TCHD-DEF
t 0
t 0
0.00 to 0.100s
&
&
&
1
Current
Reversal
detection
logic
&
&
&
DEFCF-AX
DEFCF-BX
DEFCF-CX
&
&
&
From Terminal 1
Permission signals received:
From Terminal 2
810000EBC1 DEFCAR_3PTP
800000EBC0 DEFCAR_ARCBLOCK
800000EBB0 DEFCAR_BLK
CAR_BLOCK
From Terminal 2
≥1
1
≥1
≥1
≥1
CH1-USE
1
CH2-USE
≥1
≥1
≥1
=1
=1
=1
=1
=1
=1
BOP
≥1
=1
=1
≥1
≥1
≥1
≥1
≥1
DEFCAR
&
&
&
DEFCAR_PERM1-A
DEFCAR_PERM1-B
DEFCAR_PERM1-C
DEFCAR_PERM2-A
DEFCAR_PERM2-B
DEFCAR_PERM2-C
To ECHO/EIKT
t 0
t 0
t 0
TDEFC
0.00 to 0.30s
External DEFCAR-R1
External DEFCAR-R2
Integral DEFCAR-R1-A
Integral DEFCAR-R1-B
Integral DEFCAR-R1-C
Integral DEFCAR-R2-A
Integral DEFCAR-R2-B
Integral DEFCAR-R2-C
Integral DEFCAR-R2-A
Figure 2.13-9 BOP scheme logic