Toshiba GR200 Series - (iii) Trip delay timer in main logic

6F2S1914 (0.49)
GRL200 (Soft 033 & 037)
- 43 -
Figure 2.3-2 Zero-sequence current differential element (I
in
-I
out
Plane)
The hatched area is expressed using the following equation



 
󰇟
DIFGL_Slope
󰇠
 
󰇟
DIFGL_Slope
󰇠
 


󰇟
DIFGL_Slope
󰇠
 
 
󰇟
DIFGL_Slope
󰇠
 󰇟DIFGL_I󰇠
(2.3-6)
where the I
in
should be less than two times a rated current (In); the In is defined in the
VCT of the relay (for more information with regard to the VCT, see the Chapter Technical
description: Transformer module for AC analogue input ).
(iii) Trip delay timer in main logic
The DIFGL function has a delay timer to issue a trip signal; thereby, the operation of DIFGL
function can be coordinated with the operations of the other protection relays. The delay timer
is a kind of definite time type; the user can set a delay time for setting [TDIFGL]. Figure 2.3-3
illustrates issuing the trip signal for the TRC function† together with the delay timer.
I
in
I
out
o
[DIFGL-I
]
2×I
n
Operating zone
[DIFGL-Slope]