Toshiba T1200 - A.4.8 RAM;ROM select controller; A.4.9 Keyboard data controller; A.4.10 Circuitry compatible with 8255

A.4.8 RAM/ROM select controller
This circuitry is for RAM/ROM select control on the system
board and issues RAS/CAS signals to the RAM and ROM for the
control.
RAM and ROM selection is performed by decoding the address
line data.
A.4.9 Keyboard data controller
This circuitry is to receive bit-serial data from the
keyboard controller (80C49), then the data is converted to
parallel data. If the PB7 is "on, the converted parallel
data is output to the PA, but if the PB7 is "1", the output
is disabled and the keyboard data is cleared. When the PB6
is "0", the keyboard data is inhibited but if it is "I", it
gets enabled. The keyboard data is composed of 8 bit-data
with a leading start bit total of 9 bits. When the
circuitry receives one-byte data from keyboard controller,
it inhibits from receiving more data and issues interrupt
signal (IRQl).
A.4.10 Circuitry compatible with 8255
This circuitry is compatible with the intel 8255 (PPI) chip.
It contains Port-A, B, A and some control registers.
a) Port A (I/O address = 060H)
Data setting to the register is performed by writing to
the I/O address 060H.
Getting the data from the register is performed by
reading the same address after setting "0" to bit 4 of
the mode register. Bit 4 of the mode register is usually
set to "1" (when power on reset) and the following data
is acquired when read operation is executed.
When mode register bit4 = "1"
A.4.11 DMA page register
This register is to save the upper 4 bits of the address
lines (Al9-Al6) during the DMA cycle.
This is composed of 3 sets of 4-bit registers and they are
assigned to the following I/O addresses.
A - 12